This disclosure relates generally to the field of protection of computer memory from unauthorized physical intrusion, or tampering, and more particularly to an integrated security enclosure for computer memory with improved tamper detection circuitry.
Sensitive data must be protected from access by unauthorized users. A software protection system may allow only selected users to access sensitive data through the use of passwords or other user identification methods. Security-relevant data, such as passwords and encryption keys, needs to be protected even more carefully from unauthorized access. However, software control and protection methods may not be enough to stop an experienced person from bypassing such protections and tampering with the memory components in which the security data is stored by, for example, direct interrogation of memory components containing the security data. Therefore, such memory components must be physically protected.
Tamper detection circuitry may detect physical intrusion attempts on a protected memory. If an attempted physical intrusion within a protected memory area is detected, an alarm may be given by the tamper detection circuitry, or the sensitive data stored in the protected memory may be destroyed to avoid loss of secrecy. Non-integrated tamper detection circuitry be implemented as an intrusion barrier made of a screen material or a tamper-responding matrix surrounding the chip or circuit board containing the protected memory. Tamper detection circuitry may alternately be integrated into a chip or circuit board containing the protected memory. Integrated tamper detection circuitry may be manufactured with finer resolution than non-integrated tamper detection circuitry. However, integrated tamper detection circuitry may have relatively low manufacturing variation as compared to non-integrated tamper protection circuitry. Therefore, even if physical probes that may be used for tampering do not have the resolution of state-of-the-art integrated tamper detection circuitry, the regularity and predictability of the structures that make up integrated tamper detection circuitry may limit the protections afforded by the integrated tamper detection circuitry.